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| 1 characteristics subject to change without notice 2033 8.1 10/04/01 smd1102 / 1103 / 1113 summit microelectronics, inc. ?summit microelectronics, inc., 2001 ? 300 orchard city dr., suite 131 ? campbell, ca 95008 ? phone 408-378-6461 ? fax 408-378- 6586 ? www.summitmicro.com preliminary ! ! ! ! ! complete data acquisition system " " " " " 10-bit a/d converter resolution " " " " " 75s acquisition plus conversion time " " " " " alarm limits for each input channel " " " " " auto-increment of input channels " " " " " two wire i 2 c serial data interface " " " " " system management bus (smbus) compat- ible " " " " " auto-monitor with smb alert output " " " " " low quiescent current of 50a " " " " " wide supply voltage range: 2.7v to 5.5v 10-bit data acquisition system for autonomous environmental monitoring functional block diagram features ! ! ! ! ! smd1102 " " " " " 2-channel analog input " " " " " external voltage reference input provided for absolute measurements ! ! ! ! ! SMD1103 " " " " " 3-channel analog input " " " " " reference voltage input for the a/d converter is connected to v dd for ratiometric measure- ments ! ! ! ! ! smd1113 " " " " " extended i 2 c operation " " " " " 3-channel analog input " " " " " external voltage reference input provided for absolute measurements gnd v dd converter clock scl sda 2033 bd 7.0 control logic 2-wire serial interface analog multiplexer 10-bit a/d converter e 2 prom alarm limit registers sample and hold smb alert # a in 2 x a in 1 a in 0 (1103, 1113) ref in (1102, 1113) x ce# a2 a1 a0 (1113) (1113) (1113) (1113) note: see pin configuration drawings for pinouts
!"! # $ * 0 a & %$ % & % '( & ) * + ,%-. && & !!' / 0+ 0 + &1 ++ ' 2/ 1 && ' 0 3 -3 0 4 % * & + 00* + + 0 5 0 3 * 5 0 +1 *& '5++& 0 + 3 & * ( -"! 6 5 $ 0 3 0 5& 0+ 0 & 550 $ 7+50 - # $ - # -0 0 5 8#% / 550* !9 # 3 5 " 0 0: %- 0 % ( -"! 6 5 5 ; %% / 550* - # $ - # $ - # -0 0 5 8#% / 550* " 0 0: %- 0 % ( -"! 6 5 5 ; %% / 550* !6 5 ! 0 -$ -$ - -&& 0 5 - # $ - # $ - # -0 0 5 8#% / 550* !9 # 3 5 " 0 0: %- 0 % ( -"! 6 5 5 ; %% / 550* a0 a1 a2 a in 2 a in 1 a in 0 gnd v dd ce# ref in nc smb alert # scl sda 1 2 3 4 5 6 7 14 13 12 11 10 9 8 2033 14 pcon 14-pin soic smd1113 2033 8 pcon-2 ref in a in 1 a in 0 gnd v dd smb alert # scl sda 1 2 3 4 8 7 6 5 8-pin soic smd1102 a in 2 a in 1 a in 0 gnd v dd smb alert # scl sda 1 2 3 4 8 7 6 5 8-pin soic SMD1103 2033 8 pcon-3 3 2033 8.1 10/04/01 smd1102 / 1103 / 1113 summit microelectronics, inc. * comment stresses listed under absolute maximum ratings may cause perma- nent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. temperature under bias ...................... C55c to 125c storage temperature ........................... C65c to 150c lead solder temperature (10 seconds) ............. 300 c terminal voltage with respect to gnd: all ......................................... C2v to 7v dc operating characteristics absolute maximum ratings* ( over recommended operating conditions; voltages are relative to gnd ) 2033 elect table recommended operating conditions temperature C40 o c to 85 o c. voltage 2.7v to 5.5v l o b m y sr e t e m a r a ps n o i t i d n o c ) 1 e t o n ( . n i m. p y t. x a ms t i n u v c c e g a t l o v y l p p u s7 . 25 . 5v i c c t n e r r u c y l p p u sn e p o s t u p t u o l l a3a m i b s t n e r r u c y b d n a t s , e l d i c d a , n e p o s t u p t u o l l a s s e c o r p n i e t i r w y r o m e m o n 0 5a i i l t n e r r u c e g a k a e l t u p n iv n i v o t v 0 = c c 2a i o l t u ot n e r r u c e g a k a e l t u pv t u o v o t v 0 = c c 0 1a v l o e g a t l o v w o l t u p t u o v c c i , v 5 = l o a m 1 . 2 =4 . 0 v v c c i , v 5 . 4 < l o a m 1 =2 . 0 v h o e g a t l o v h g i h t u p t u o v c c i , v 5 = l o a 0 0 4 ? = 4 . 2 v v c c i , v 5 . 4 < l o a 0 0 1 ? =v c c 2 . 0 ? v l i e g a t l o v w o l t u p n i1 . 0 ? 3 . 0 v c c v v h i e g a t l o v h g i h t u p n i7 . 0 v c c v c c 7 . 0 +v s t u p n i g o l a n a v n i f e r v f e r e g a t l o v t u p n i1v c c v v n i a n o e g a t l o v t u p n i n i 0 a h g u o r h t n i 2 05 . 5v 4 smd1102 / 1103 / 1113 2033 8.1 10/04/01 summit microelectronics, inc. pin descriptions serial clock (scl) the scl input is used to clock data into and out of the device. in the write mode data must remain stable while scl is high. in the read mode data is clocked out on the falling edge of scl. serial data (sda) the sda pin is a bidirectional pin used to transfer data into and out of the device. data may change only when scl is low, except during start and stop conditions. it is an open-drain output and may be wire-ored with any number of open-drain or open-collector outputs. smb alert # this interrupt output pin signals the host when an out-of- limit condition is detected by one of the eeprom limit registers. the smb alert open-drain output is active low. ref in voltage reference input for 10-bit a/d converter. this signal is only on the smd1102 and smd1113. a in 0, a in 1, a in 2 multiplexer input pins for channels 0, 1, and 2, respec- tively. a in 2 is only available on the SMD1103 and smd1113. these pins may be left unconnected if they are not used. however, the alert regions must be set accordingly (see the section "alert conditions"). a0, a1, a2 the address inputs are only available on the smd1113. multiple smd1113s can be used on a single bus by setting different device addresses. a2 has a 50k ? pull-up resistor, and a1 and a0 have 50k ? pull-down resistors. do not set the address to all zeroes because it would cause a conflict with the smb alert response. ce# chip enable/disable input must be held low to enable i 2 c communications. it has a 50k ? pull-down resistor and is only available on the smd1113. v dd power supply input. gnd power supply return. 5 2033 8.1 10/04/01 smd1102 / 1103 / 1113 summit microelectronics, inc. device operation the smd1102, SMD1103 and smd1113 data acquisition systems (das) are each comprised of: an analog input multiplexer, sample-and-hold circuit, 10-bit successive approximation analog-to-digital (a/d) converter, and nonvolatile eeprom memory to store upper and lower alarm-limits for each input channel. the user programs the alarm limits via the industry-standard i 2 c interface. an smb alert # interrupt output signals if any of the analog inputs move outside these limits. das modes of operation the smd1102/1103/1113 have four user-selectable modes of operation. these modes are: a single conver- sion of one channel, successive conversions on the same channel, sequential conversions on all three channels, or autonomous conversions of the same or all channels. sample-and-hold operation the channel switching and sampling architecture of the a/ ds comparator is illustrated in the equivalent input circuit diagram in figure 1. during acquisition the selected channel charges a capacitor in the sample-and-hold cir- cuit. the acquisition interval spans the acknowledge period following the command byte and ends on the rising edge of the next clock. at the end of the acquisition phase the analog input is disconnected, retaining charge on the hold capacitor as a sample of the signal. figure 1. sample/hold and sar + ? 2033 fig01 2.0 analog in buffer dac sar sample & hold sda the next bit in the addressing sequence is the eeprom/ conversion (e/c) bit; when set to zero the device is instructed to perform an a/d conversion, and when set to logic one the eeprom limit register will be addressed. see table 1a. the next two bits are the channel select bits. auto- increment is enabled if the channel select bits are set to 11 bin and the conversion bit is set to zero. in the auto- increment mode conversions are performed on succes- sive channels, starting with channel 0. after channel 2 is converted (channel 1 on the smd1102) the address will wrap around to channel 0. see table 1b. the last bit is the read/monitor bit. when the bit is set to logic one, data can be read from a conversion or from one of the eeprom limit registers, depending on the state of the eeprom/conversion bit. when the bit is logic zero either the auto-monitor mode is entered or the eeprom limit register is programmed, again depending on the state of the eeprom/conversion bit. see table 1c. addressing and command sequence all operations of the das are preceded first by the start condition and then by the addressing command se- quence. for the smd1102 & SMD1103 this is 1001 bin. for the smd1113 it is the binary values of a2, a1, a0, and a one a four bit number. table 1a. address byte eeprom/conversion 7 b d6 b d5 b d4 b d3 b d n o i t c n u f r e i f i t n e d i e p y t e c i v e dc / e 2 a r o * 1 1 a r o * 0 0 a r o * 0 1 0 - n o c d / a m r o f r e p d e t c e l e s n o n o i s r e v ) s ( l e n n a h c 1 m o r p e e s s e r d d a r e t s i g e r t i m i l 2033 table01a * denotes smd 1102 & SMD1103. ax bits are for the smd1113. table 1b. address byte channel select 2033 table01b * denotes smd 1102 & SMD1103. ax bits are for the smd1113. 7 b d6 b d5 b d4 b d2 b d1 b d n o i t c n u f r e i f i t n e d i e p y t e c i v e d1 h c0 h c 2 a r o * 1 1 a r o * 0 0 a r o * 0 1 00 0 l e n n a h c d e t c e l e s 01 1 l e n n a h c d e t c e l e s 10 2 l e n n a h c d e t c e l e s 11 f i t n e m e r c n i - o t u a 0 = c / e 6 smd1102 / 1103 / 1113 2033 8.1 10/04/01 summit microelectronics, inc. single channel conversions this command sequence is composed of: the device type identifier, followed by the e/c bit set to zero, then the channel select bits set to the desired value, and the r/m bit set to logic one. after the r/m bit is clocked in the host releases the sda line and monitors the sda line for an acknowledge bit (ack) from the smd1102/1103/1113. the device will drive the sda line low indicating it received the command and that it has initiated the acquisition and conversion on the selected channel. the clock source for the acquisition and conversion is an internal clock. after the ack the smd1102/1103/1113 will output four dummy zeros on sda followed by an echo of the channels 2 address bits. the remaining bits in this first byte are the two msbs of the conversion. refer to figure 2 for a detailed illustration of this sequence, and for that of retrieving the remaining conversion byte. the host can issue a stop condition after retrieving the conversion data and place the smd1102/1103/1113 in a low power standby mode. successive single channel conversions if the host does not issue a stop command after receiving the last bit of the previous conversion, but instead issues an ack and continues clocking, then the smd1102/1103/ 1113 will begin another acquisition and conversion pro- cess on the same channel. auto-increment in the auto-increment mode, the das starts a conversion and then automatically advances to the next channel. the auto-increment mode always starts at channel 0 and switches the channel input in the sequence 0, 1, 2, 0, 1, 2, etc. after each successive conversion. the smd1102, SMD1103, and smd1113 independently repeat this pro- cess so long as the host continues clocking the device, supplies ack bits at the appropriate clock interval, and issues no stop conditions. refer to figure 4 for a detailed illustration of the sequence. programming the limit registers programming the nonvolatile limit registers of the smd1102/1103/1113 for use with the auto-monitor func- tion is straightforward. associated with each channel is an 11-bit lower limit register and an 11-bit upper limit register. ten bits correspond to the 10-bit data, and the msb represents the monitor option bit. the monitor option bits of the upper and lower limit combine to define the alert region for each channel (described more fully in the section labeled alert conditions). each limit register must be programmed separately with a three byte com- mand sequence. to program the limit register the host first issues a start condition, followed by the device type identifier, the eeprom/conversion (e/c) bit (set to one), the channel select bits, and the read/monitor bit (set to zero). the second byte consists of four zeroes followed by the limit select bit (zero = lower limit, one = upper limit), the monitor option bit, and the two most significant bits of the limit data. the third byte consists of the remaining eight bits of limit data. after receiving a stop condition, the smd1102/1103/1113 initiates its internal program sequence. refer to figure 5 for details. six such sequences are required to set the upper and lower limits for all three channels. however, once programmed the data remains stored in eeprom until reprogrammed. for example, when a device has both v dd and v ref at 5.00v, and an alert must be generated if the voltage on any channel is 2.00v or >3.00v, then the monitor option bits are set to 10 bin , the upper limit is set to 266 hex , and the lower limit is set to 199 hex . reading the limit registers the timing diagram for reading the limit register data of a particular channel is shown in figure 6. the five byte sequence commences with a start condition, followed by the device type identifier, the eeprom/conversion bit (set to one), the channel select bits, and the read/monitor bit (set to one). after acknowledging the slave byte the device outputs a one, followed by an echo of the channel select bits, a zero, another zero (representing the lower limit data), the monitor option bit and the two most significant bits of the limit data. the third byte consists of the remaining eight bits of the lower limit data. the fourth byte of the output sequence is the same as the second byte except the fifth bit is a one (to indicate upper 2033 table01c table 1c. address byte read/monitor * denotes smd 1102 & SMD1103. ax bits are for the smd1113. 7 b d6 b d5 b d4 b d0 b d n o i t c n u f r e i f i t n e d i e p y t e c i v e dm / r 2 a r o * 1 1 a r o * 0 0 a r o * 0 1 0 r o t i n o m - o t u a e l b a n e m o r p e e e t i r w r o c / e ( r e t s i g e r t i m i l ) e t a t s 1 - n o c d / a d a e r m o r p e e r o n o i s r e v c / e ( r e t s i g e r t i m i l ) e t a t s 7 2033 8.1 10/04/01 smd1102 / 1103 / 1113 summit microelectronics, inc. figure 4. auto-increment continuous read sequence figure 5. programming the auto-monitor limit registers figure 6. reading the auto-monitor limit registers monitor option upper/lower 1 0 0 u/l 0 0 0 0 a c k s t a r t a c k a c k s t o p d9 op0 1 e/c ch1 ch0 d8 d7 d6 d5 d4 d3 d2 d1 d0 r/m 2033 fig05 channel address scl sda device type identifier figure 2. single channel read sequence channel address echo 1 0 0 ch1 a c k s t a r t a c k a c k d9 ch0 0 0 00 1 e/c ch1 ch0 d8 d7 d6 d5 d4 d3 d2 d1 d0 r/m 2033 fig03 3.0 channel address ch1 a c k d9 ch0 0 conversion #2 0 0 0 d8 d7 d6 conversion #1 channel address scl sda device type identifier figure 3. single channel continuous read sequence channel address echo 1 0 0 ch1 a c k s t a r t a c k n a c k s t o p d9 ch0 0 0 00 1 e/c ch1 ch0 d8 d7 d6 d5 d4 d3 d2 d1 d0 r/m 2033 fig02 channel address scl sda device type identifier monitor option lower limit 100 0 a c k s t a r t a c k a c k d9 op0 1 1 ch1 ch0 d8 d7 d6 d5 d4 d3 d2 d1 d0 r/m scl sda 2033 fig06 1 ch1 ch0 0 monitor option upper limit 1 a c k d9 op0 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 ch1 ch0 0 n a c k s t o p channel 0 address echo 1 0 0 ch1 a c k s t a r t a c k a c k d9 ch0 0 0 00 1 ch1 ch0 d8 d7 d6 d5 d4 d3 d2 d1 d0 r/m 2033 fig04 channel 1 address ch1 a c k d9 ch0 0 conversion #2 channel 1 0 0 0 d8 d7 d6 conversion #1 channel 0 channel address = 11 scl sda device type identifier e/c 8 smd1102 / 1103 / 1113 2033 8.1 10/04/01 summit microelectronics, inc. stored with the upper and lower limits in the nv registers. figure 8 details these conditions. if an out-of-limit condition is detected the smd1102/1103/1113 will tempo- rarily remove itself from the auto-increment mode (if that was selected), and monitor the channel that caused the alert. there must be five successive conversions result- ing in an out-of-limit condition before the smd1102/1103/ 1113 will signal an alert. if at any time during the verify routine the out-of-limit condition is negated the smd1102/ 1103/1113 will re-enter its auto-monitor routine. if a valid alert condition has been detected the device will halt the auto-monitor function and await instructions from the host. if any one of the channels is not being used while the auto- monitor function is enabled that channel must have its alert conditions as well as its limit registers set so that it does not cause an alert. this is accomplished by first setting the alert region inside the limits ( i.e. , set monitor option bits to either 10 bin or 11 bin ), and then setting the lower limit above the upper limit. alert response the smd1102, SMD1103 and smd1113 are considered slave devices. they do not generate clocks on the scl pin or take control of bus activity. however, the smbus specification, an extension of the i 2 c specification, does allow slave devices the ability to generate interrupts to get the attention of the host by pulling smb alert # low. after the smd1102/1103/1113 has issued an alert by pulling smb alert # low the alert can only be reset by addressing the device. if there is more than one device on the smbus capable of generating an alert, the host may determine the offending device by issuing an alert re- sponse address (ara). the ara is a general call to all devices, but only an smbus compatible device will recog- nize the call, and only a device that generated an interrupt will respond to the call. the das responds by acknowl- edging the ara, and then by sending its device address on the sda line, as shown in figure 9. embedded in the device address is the channel that caused the alert. if more than one smbus compliant device has responded to the ara, standard i 2 c bus arbitration allows the device with the lowest address to be serviced first. note: the device address of an smd1113 should not be set with a2, a1 and a0 all equal to zero. this would create an address conflict with the smb alert # broadcast message. figure 7. begin auto-monitor command 100 a c k s t a r t 10 ch1 ch0 0 2033 fig07 channel address scl sda device type identifier s t o p limit data is forthcoming), and the data bits are from the upper limit. the fifth and final byte represents the remaining eight bits of the upper limit data. auto-monitor auto-monitor operation takes full advantage of the unique capabilities of the smd1102/1103/1113. each device can autonomously monitor the analog channels, compare the conversion data against stored, nonvolatile limit regis- ters, and, if necessary, alert the host to out-of-limit conditions. the command string to enter the auto- monitor mode is shown in figure 7. it consists of a start condition followed by the device type identifier (slave address), the eeprom/conversion bit set to zero, the channel select bits, and the read/monitor bit set to zero. after acknowledge the host issues a stop condition in order to initiate the auto-monitor process. setting the channel select bits to a particular channel limits the monitoring to that channel. setting the channel select bits to 11 allows all three inputs to be monitored in succes- sion (auto-increment). in the case of the 1102 the limit registers for channel 2 should be set so that the alert cannot be generated from this channel (see the following section "alert conditions"). the auto-monitor operation must be terminated before further communication with the device. the auto-monitor function is automatically shut down when an alert is asserted. any read operation will also halt auto-monitor, and, if an alert has occurred, it will clear the alert along with the stored information of the channel that prompted the alert. note: a read operation that is used to halt the auto-monitor function will not return valid data. alert conditions for each channel the host can select one of four condi- tions that will generate an alert while auto-monitor is active. these conditions are determined by the option bits 9 2033 8.1 10/04/01 smd1102 / 1103 / 1113 summit microelectronics, inc. figure 10. resetting smb alert # figure 8. four alert conditions figure 9. smb alert # response sequence 001 1 a c k n a c k s t a r t s t o p 0 ch1 ch0 2033 fig10 scl smb alert # sda r/m once the smb alert # signal has been asserted it must be reset before further communication with the device, with the exception of the smb alert # response sequence. resetting the smb alert # is accomplished by performing a read operation. figure 10 shows the smb alert # signal being reset by a read operation. note: a read operation that is used to reset the smb alert # will not return valid data. monitor option bits x x lower upper 2033 fig08 alert region alert region alert region alert region 3ff solid line indicates alert set if conv = limit upper limit dashed line indicates alert not set if conv = limit 000 "00" "01" "10" "11" 3ff 000 alert region alert region 3ff 000 3ff 000 lower limit device type identifier 001 0 ch1 a c k n a c k s t a r t s t o p ch0 10 0 1 1 00 0 r/m 2033 fig09 alert response address scl smb alert # sda offending channel address 10 smd1102 / 1103 / 1113 2033 8.1 10/04/01 summit microelectronics, inc. table 2. register read/write ac operating characteristics general description the i 2 c bus is a two-way, two-line serial communication between different integrated circuits. the two lines are: a serial data line (sda) and a serial clock line (scl). all summit microelectronics parts support a 100khz clock rate, and some support the alternative 400khz clock. check table 2 for the value of f scl . the sda line must be connected to a positive supply by a pull-up resistor located on the bus. summit parts have a schmitt input on both lines. see figure 11 and table 2 for waveforms and timing on the bus. one bit of data is transferred during each clock pulse. the data must remain stable when the clock is high. bus interface 2033 table02 figure 11. interface bus timing l o b m y sr e t e m a r a ps n o i t i d n o c. n i m. x a ms t i n u f l c s y c n e u q e r f k c o l c l c s 00 0 1z h k t w o l d o i r e p w o l k c o l c 7 . 4s t h g i h d o i r e p h g i h k c o l c 0 . 4s t f u b ) 1 ( e m i t e e r f s u bn o i s s i m s n a r t w e n e r o f e b7 . 4s t a t s : u s e m i t p u t e s n o i t i d n o c t r a t s 7 . 4s t a t s : d h e m i t d l o h n o i t i d n o c t r a t s 0 . 4s t o t s : u s e m i t p u t e s n o i t i d n o c p o t s 7 . 4s t a a t u p t u o d i l a v o t e g d e k c o l c) n e l c y c ( a d s d i l a v o t w o l l c s3 . 05 . 3s t h d ) 1 ( e m i t d l o h t u o a t a de g n a h c a d s o t ) 1 + n e l c y c ( w o l l c s3 . 0s t r ) 1 ( e m i t e s i r a d s d n a l c s 0 0 0 1s n t f ) 1 ( e m i t l l a f a d s d n a l c s 0 0 3s n t t a d : u s ) 1 ( e m i t p u t e s n i a t a d 0 5 2s n t t a d : d h ) 1 ( e m i t d l o h n i a t a d 0s n i t) 1 ( a d s d n a l c s r e t l i f e s i o nn o i s s e r p p u s e s i o n0 0 1s n t r w e m i t e l c y c e t i r w 5s m note (1) these values are guaranteed by design. t f t r t low t high t hd:sta t su:sta t buf t dh t hd:dat t su:dat t su:sto scl sda in sda out t aa 2033 fig11 11 2033 8.1 10/04/01 smd1102 / 1103 / 1113 summit microelectronics, inc. start and stop conditions both data and clock lines remain high when the bus is not busy. data transfer between devices may be initiated with a start condition only when scl and sda are high. a high- to-low transition of the data line while the clock line is high is defined as a start condition. a low-to-high transition of the data line while the clock line is high is defined as a stop condition. see figure 12. acknowledge data is always transferred in 8-bit bytes. acknowledge (ack) is used to indicate a successful data transfer. the transmitting device will release the bus after transmitting eight bits. during the ninth clock cycle the receiver will pull the sda line low to acknowledge that it received the eight bits of data (see figure 13). the termination of a master read sequence is indicated by a non-acknowl- edge (nack), where the master will leave the data line high. in the case of a read from a summit part, when the last byte has been transferred to the master, the master will leave the data line high for a nack. this will cause the summit part to stop sending data, and the master will issue a stop on the clock pulse following the nack. in the case of a write to a summit part the master will send a stop on the clock pulse after the last acknowledge. this will indicate to the summit part that it should begin its internal nonvolatile write cycle. read and write the first byte from a master is always made up of the eight bits illustrated in table 1. in the read mode the smd1102/1103/1113 transmits eight bits of data, then releases the sda line, and monitors the line for an acknowledge signal. if an acknowledge is detected, and no stop condition is generated by the master, the device will continue to transmit data. if an acknowledge is not detected (nack), the device will terminate further data transmission. in the write mode the smd1102/1103/1113 receives eight bits of data, then generates an acknowledge signal. it will continue to generate acks until a stop condition is generated by the master. protocol the protocol defines any device that sends data onto the bus as a transmitter, and any device that receives data as a receiver. the device controlling data transmission is called the master, and the controlled device is called the slave. in all cases the summit microelectronic devices are slave devices, since they never initiate any data transfers. 2033 fig10 scl sda in start condition stop condition figure 12. start and stop conditions figure 13. acknowledge timing scl sda trans sda rec 1 2 3 8 9 ack 2033 fig11 1 2 sm d1102 / 1103 / 111 3 2033 8.1 10/04/0 1 summi t microelec t ronics, inc . package s .228 (5.80) .244 (6.20) .016 (.40) .035 (.90) .020 (.50) .010 (.25) x45 .0192 (.49) .0138 (.35) .061 (1.75) .053 (1.35) .0098 (.25) .004 (.127) .05 (1.27) typ. .275 (6.99) typ. .030 (.762) typ. 8 places .050 (1.27) typ. .050 (1.270) typ. 8 places .157 (4.00) .150 (3.80) .196 (5.00) 1 .189 (4.80) footprint 8pn jedec soic ill.2 8 pin soic (type s) package jedec (150 mil body width) !"! # $ ,* *& @&a 0.150 - 0.157 0.013 - 0.020 (0.33 - 0.51) 0.004 - 0.01 (0.10 - 0.25) 0.337 - 0.344 (8.55 - 8.75) 0.228 - 0.244 (5.80 - 6.20) 0.053 - 0.069 (1.35 - 1.75) 0.016 - 0.050 (0.40 - 1.27) (1.27) 0.0075 - 0.01 (0.19 - 0.25) 0.01 - 0.02 (0.25 - 0.50) (3.80 - 4.00) 14 pin soic 45 o !"! # $ # ! 0 $ 1 +: 5& & 5 0 & +51 & $ 53+ 0 0 * 0 $ + 5 0 * 3 3 * & & $ 1* 0 & * 5 $ & +: 5 3 3 5 3 + & & 0 & 30 5 1 5 5+ $ & +* 1* &5& 5 e 5 3 550 b 0 3+ 5 0 3 00* :&$ 0 $ 00 0 0 3 * &+ 0 3 * + 0 $ & ++& 3 * 3 5& 0 3 55 1 550 3 0 +03 3 5& 0* 75& * 3 0 3 * + 3 0* 33 3* 33 1 /& 4& 3 550 0 0 $ 1 $ 3 $ @ ,. : 3 * &+ + + 4&f , . + 00 : f & ,. 5 0 0 0 * 3 0 $ &) 0* 5& & + & + 5 & 00 51 1 p 5* 0 $ &+: 3 / 0 5 5 *& &@ a . summit smd1113s l yy ww package type - soic (s) l = lot number yy = year ww = work week smd1113 . summit SMD1103 s l yy ww package type - soic (s) l = lot number yy = year ww = work week . summit SMD1103 s l yy ww 02 smd1102 SMD1103 |
Price & Availability of SMD1103
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